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The Digi NS7520 is a high-performance, highly integrated, 32-bit system-on-a chip ASIC designed for use in intelligent networked devices and Internet appliances. The NS7520 is based on the standard architecture in the NET+ARM™ family of devices.
The NS7520 can support most any networking scenario, and includes a 10/100 BaseT Ethernet MAC and two independent serial ports (each of which can run in UART or SPI mode).
The CPU is an ARM7TDMI 32-bit RISC processor core with a rich complement of support peripherals and memory controllers for various types of memory (including Flash, SDRAM, EEPROM, and others), programmable timers, a 13-channel DMA controller, an external bus expansion module, and 16 general-purpose input/output (GPIO) pins.
NET+ARM is the hardware foundation for the NET+Works™ family of integrated hardware and software solutions for device networking. These comprehensive platforms include drivers, popular operating systems, networking software, development tools, APIs, and complete development boards.
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Features
CPU core:
- ARM7TDMI 32-bit RISC processor
- 32-bit internal bus
- 32-bit ARM and 16-bit Thumb mode
- 15 general purpose 32-bit registers
- 32-bit program counter (PC) and status register
- Five supervisor modes, one user mode
13-Channel DMA controller:
- Two channels dedicated to Ethernet transmit and receive
- Four channels dedicated to two serial modules’ transmit and receive
- Four channels for external peripherals. Only two channels — either 3 and 5 or 4 and 6 — can be configured at one time
- Three channels available for memory-to-memory transfers
- Flexible buffer management
General purpose I/O pins:
- 16 programmable GPIO interface pins
- 4 pins programmable with level-sensitive interrupt
Integrated 10/100 Ethernet MAC: - 10/100 Mbps MII-based PHY interface
- 10 Mbps ENDEC interface
- TP-PMD and fiber-PMD device support
- Full-duplex and half-duplex modes
- Optional 4B/5B coding
- Station, broadcast, and multicast address detection
- 512-byte transmit FIFO, 2 Kbyte receive FIFO
- Intelligent receive-side buffer selection
Programmable Timers: - Two independent timers (2μs–20.7 hours)
- Watchdog timer (interrupt or reset on expiration)
- Programmable bus monitor or timer
Operating Frequency:
- 36, 46, or 55 MHz internal clock operation from 18.432 MHz crystal
- fMAX = 36, 46, or 55 (grade–dependent)
- System clock source by external quartz crystal or crystal oscillator, or clock signal
- Programmable PLL, which allows a range of operating frequencies from 10 to fMAX
- Maximum operating frequency from external clock or using PLL multiplication fMAX
Serial ports:
- Two fully independent serial ports (UART, SPI)
- Digital phase lock loop (DPLL) for receive clock extractions
- 32-byte transmit/receive FIFOs
- Internal programmable bit-rate generators
- Bit rates 75–230400 in 16X mode
- Bit rates 1200 bps–4 Mbps in 1X mode
- Flexible baud rate generator, external clock for synchronous operation
- Receive-side character and buffer gap timers
- Four receive-side data match detectors
Power and Operating Voltages:
- 500 mW maximum at 55 MHz (all outputs switching)
- 418 mW maximum at 46 MHz (all outputs switching)
- 291 mW maximum at 36 MHz (all outputs switching)
- 3.3 V — I/O
- 1.5 V — Core
Bus interface:
- Five independent programmable chip selects with 256 Mb addressing per chip select
- Chip select support for SRAM, FP/EDO DRAM, SDRAM, Flash, and EEPROM without external glue
- 8-, 16-, and 32-bit peripheral support
- External address decoding and cycle termination
- Dynamic bus sizing
- Internal DRAM/SDRAM controller with address multiplexer and programmable refresh frequency
- Internal refresh controller (CAS before RAS)
- Burst-mode support
- 0–63 wait states per chip select
- Address pins that configurem chip operating modes (see "NS7520 bootstrap initialization" on page 22 of DS)
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