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Features
32-bit ARM926EJ-S RISC processor:
- 103 to 177 MHz
- 5-stage pipeline with interlocking
- Harvard architecture
- 8 kB instruction cache and 4 kB data cache
- 32-bit ARM and 16-bit Thumb instruction sets. Can be mixed for performance/code density tradeoffs
- MMU to support virtual memory-based OSs such as Linux, WinCE/Pocket PC, VxWorks, others
- DSP instruction extensions, improved divide, single cycle MAC
- ARM Jazelle, 1200CM (coffee marks) Java accelerator
- EmbeddedICE-RT debug unit
- JTAG boundary scan, BSDL support
External system bus interface:
- 32-bit data, 32-bit internal address bus, 28-bit external address bus
- Glueless interface to SDRAM, SRAM, EEPROM, buffered DIMM, Flash
- 4 static and 4 dynamic memory chip selects
- 1-32 wait states per chip select (A shared Static Extended Wait register allows transfers to have up to 16368 wait states that can be externally terminated.)
- Self-refresh during system sleep mode
- Automatic dynamic bus sizing to 8 bits, 16 bits, 32 bits
- Burst mode support with automatic data width adjustment
- Two external DMA channels for external peripheral support
System Boot:
- High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash
- Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending)
High performance 10/100 Ethernet MAC:
- 10/100 Mbps MII/RMII PHY interfaces
- Full-duplex or half-duplex
- Station, broadcast, or multicast address filtering
- 2 kB RX FIFO
- 256 byte TX FIFO with on-chip buffer descriptor ring
- Eliminates underruns and decreases bus traffic
- Separate TX and RX DMA channels
- Intelligent receive-side buffer size selection
- Full statistics gathering support
- External CAM filtering support
Flexible LCD controller:
- Supports most commercially available displays:
- 18-bit active Matrix color TFT displays
- Single and dual panel color STN displays
- Single and dual-panel monochrome STN displays
- Formats image data and generates timing control signals
- Internal programmable palette LUT and grayscaler support different color techniques
- Programmable panel-clock frequency
USB ports:
- USB v.2.0 full speed (12 Mbps) and low speed (1.5 Mbps)
- Independent OHCI Host and Device ports
- Internal USB PHY
- External USB PHY interface
- USB device supports one bidirectional control endpoint and 10 unidirectional endpoints
- All endpoints supported by a dedicated DMA channel
- 32 byte FIFO per endpoint
Serial ports:
- 4 serial modules, each independently configurable to UART mode, SPI master mode, or SPI slave mode
- Bit rates from 75 bps to 921.6 kbps: asynchronous x16 mode
- Bit rates from 1.2 kbps to 11.25 Mbps: synchronous mode
- UART provides:
- High-performance hardware and software flow control
- Odd, even, or no parity
- 5, 6, 7, or 8 bits
- 1 or 2 stop bits
- Receive-side character and buffer gap timers
- Internal or external clock support, digital PLL for RX clock extraction
- 4 receive-side data match detectors
- 2 dedicated DMA channels per module, 8 channels total
- 32 byte TX FIFO and 32 byte RX FIFO per module
I2C port:
- I2C v.1.0, configurable to master or slave mode
- Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching
- 7-bit and 10-bit address modes
- Supports I2C bus arbitration
1284 parallel peripheral port:
- All standard modes: ECP, byte, nibble, compatibility (also known as SPP or “Centronix”)
- RLE (run length encoding) decoding of compressed data in ECP mode
- Operating clock from 100 kHz to 2 MHz
High performance multiple-master/distributed DMA system:
- Intelligent bus bandwidth allocation (patent pending)
- System bus and peripheral bus
System bus:
- Every system bus peripheral is a bus master with a dedicated DMA engine
Peripheral bus:
- One 12-channel DMA engine supports USB device
- 2 DMA channels support control endpoint
- 10 DMA channels support 10 endpoints
- One 12-channel DMA engine supports:
- 4 serial modules (8 DMA channels)
- 1284 parallel port (4 DMA channels)
- All DMA channels support fly-by mode
External peripheral:
- One 2-channel DMA engine supports external peripheral connected to memory bus
- Each DMA channel supports memory-to-memory transfers
Power management (patent pending)
- Power save during normal operation
- Power save during sleep mode
- Sets memory controller to refresh
- Disables all modules except selected wakeup modules
- Wakeup on valid packets or characters
Vector interrupt controller
- Decreased bus traffic and rapid interrupt service
- Hardware interrupt prioritization
General purpose timers/counters
- 8 independent 16-bit or 32-bit programmable timers or counters
- Mode selectable into:
- Internal timer mode
- External gated timer mode
- External event counter
- Can be concatenated
- Resolution to measure minute-range events
- Source clock selectable: internal clock or external pulse event
- Each can be individually enabled/disabled
System timers
- Watchdog timer
- System bus monitor timer
- System bus arbiter timer
- Peripheral bus monitor timer
General purpose I/O
- 73 programmable GPIO pins (muxed with other functions)
- Software-readable powerup status registers for every pin for customer-defined bootstrapping
External interrupts
- 4 external programmable interrupts
- Rising or falling edge-sensitive
- Low level- or high level-sensitive
Clock generator
- Low cost external crystal
- On-chip phase locked loop (PLL)
- Software programmable PLL parameters
- Optional external oscillator
- Separate PLL for USB
Operating grades/Ambient temperatures
- 177 MHz: 0 – 70° C
- 155 MHz: -40 – +85° C
- 103 MHz: 0 – 70° C
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